1. Technical Field
The present invention relates to thin film transistor semiconductor device based on carbon nanotubes and method for making the same.
2. Description of Related Art
Single-walled carbon nanotubes (SWCNTs) are promising candidates for future electronic devices because of their excellent electrical and mechanical properties, including high mobility, large current density, and extremely good mechanical strength. In particular, because of their uniformity and repeatability, thin film transistors (TFTs) with SWCNT random networks as conductive channels have been widely studied. Meanwhile, depositing or printing pre-separated semiconducting SWCNTs or transferring networks grown by chemical vapor deposition onto flexible substrates can meet the needs of flexible and wearable electronic devices.
SWCNT-TFTs show p-type characteristics in ambient conditions because of the adsorption of oxygen and water vapor. Although many applications, such as logic circuits, memory devices, sensors, or even computers, are fabricated by p-type TFTs, complementary metal oxide semiconductor (CMOS) circuits including a couple of n-type and p-type TFTs are still demanded urgently because of their low static power consumption and large noise margin. To date, several methods have been investigated to achieve high performance n-type SWCNT-TFTs, but most of them have difficulties in integration with p-type devices. For example, doping SWCNT channels with alkali metal such as potassium (K), or organic polymers such as Polyetherimide (PEI) and viologen can lead to high-performance n-type TFTs. However, alkali metal and organic polymers are unstable and flowable, which may contaminate the nearby exposed p-type TFTs, which means that sparse integration is required. Another approach is covering high-κ oxide such as hafnium oxide using atomic layer deposition (ALD) or passivation with a silicon nitride film using plasma-enhanced chemical vapor deposition (PECVD) as the dielectric layer to isolate oxygen and water, as well as electron doping. However, the covering materials are all compact and grown at a relatively high temperature beyond the photoresist endurance, the positions of the dopant have to be defined using a relatively large size shadow mask instead of standard photolithography, leading to jumbo size devices as a result.
What is needed, therefore, is a method of integrating n-type and p-type TFTs compactly, massively, and stably that can overcome the above-described shortcomings.